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? 2005 fairchild semiconductor corporation ds500065 www.fairchildsemi.com october 1997 revised june 2005 74VCX16373 low voltage 16-bit transparent latch with 3.6v tolerant inputs and outputs 74VCX16373 low voltage 16-bit transparent latch with 3.6v tolerant inputs and outputs general description the vcx16373 contains sixteen non-inverting latches with 3-state outputs and is intended for bus oriented applica- tions. the device is byte controlled. the flip-flops appear to be transparent to the data when the latch enable (le) is high. when le is low, the data that meets the setup time is latched. data appears on the bus when the output enable (oe ) is low. when oe is high, the outputs are in a high impedance state. the 74VCX16373 is designed for low voltage (1.2v to 3.6v) v cc applications with i/o compatibility up to 3.6v. the 74VCX16373 is fabricated with an advanced cmos technology to achieve high speed operation while maintain- ing low cmos power dissipation. features 1.2v to 3.6v v cc supply operation 3.6v tolerant inputs and outputs t pd (i n to o n ) 3.0 ns max for 3.0v to 3.6v v cc power-off high impedance inputs and outputs support live insertion and withdrawal (note 1) static drive (i oh /i ol ) r 24 ma @ 3.0v v cc latch-up performance exceeds 300 ma esd performance: human body model ! 2000v machine model ! 200v also packaged in plastic fine-pitch ball grid array (fbga) (preliminary) note 1: to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ordering code: note 2: ordering code g indicates trays. note 3: devices also available in tape and reel. specify by appending suffix letter x to the ordering code. logic symbol order number package number package description 74VCX16373g (note 2)(note 3) bga54a (preliminary) 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide 74VCX16373mtd (note 3) mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide uses proprietary noi se/emi reduction circuitry
www.fairchildsemi.com 2 74VCX16373 connection diagrams pin assignment for tssop pin assignment for fbga (top thru view) pin descriptions fbga pin assignments truth tables h high voltage level l low voltage level x immaterial (high or low, inputs may not float) z high impedance o 0 previous o 0 before high-to-low of latch enable pin names description oe n output enable input (active low) le n latch enable input i 0 Ci 15 inputs o 0 Co 15 outputs nc no connect 123456 a o 0 nc oe 1 le 1 nc i 0 b o 2 o 1 nc nc i 1 i 2 c o 4 o 3 v cc v cc i 3 i 4 d o 6 o 5 gnd gnd i 5 i 6 e o 8 o 7 gnd gnd i 7 i 8 f o 10 o 9 gnd gnd i 9 i 10 g o 12 o 11 v cc v cc i 11 i 12 h o 14 o 13 nc nc i 13 i 14 j o 15 nc oe 2 le 2 nc i 15 inputs outputs le 1 oe 1 i 0 Ci 7 o 0 Co 7 xhxz hlll hlhh llxo 0 inputs outputs le 2 oe 2 i 8 Ci 15 o 8 Co 15 xhxz hlll hlhh llxo 0
3 www.fairchildsemi.com 74VCX16373 functional description the 74VCX16373 contains sixteen edge d-type latches with 3-state outputs. the device is byte controlled with each byte functioning identically, but independent of the other. control pins can be shorted together to obtain full 16-bit operation. the following description applies to each byte. when the latch enable (le n ) input is high, data on the i n enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its i input changes. when le n is low, the latches store information that was present on the i inputs a setup time preceding the high-to-low transition on le n . the 3-state outputs are controlled by the output enable (oe n ) input. when oe n is low the standard outputs are in the 2-state mode. when oe n is high, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays.
www.fairchildsemi.com 4 74VCX16373 absolute maximum ratings (note 4) recommended operating conditions (note 6) note 4: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rat- ings. the recommended operating conditions table will define the condi- tions for actual device operation. note 5: i o absolute maximum rating must be observed. note 6: floating or unused inputs must be held high or low. dc electrical characteristics supply voltage (v cc ) 0.5v to 4.6v dc input voltage (v i ) 0.5v to 4.6v output voltage (v o ) outputs 3-stated 0.5v to 4.6v outputs active (note 5) 0.5v to v cc 0.5v dc input diode current (i ik ) v i 0v 50 ma dc output diode current (i ok ) v o 0v 50 ma v o ! v cc 50 ma dc output source/sink current (i oh /i ol ) r 50 ma dc v cc or gnd current per supply pin (i cc or gnd) r 100 ma storage temperature range (t stg ) 65 q c to 150 q c power supply operating 1.2v to 3.6v input voltage 0.3v to 3.6v output voltage (v o ) output in active states 0.0v to v cc output in off state 0.0v to 3.6v output current in i oh /i ol v cc 3.0v to 3.6v r 24 ma v cc 2.3v to 2.7v r 18 ma v cc 1.65v to 2.3v r 6 ma v cc 1.4v to 1.6v r 2 ma v cc 1.2v r 100 ma free air operating temperature (t a ) 40 q c to 85 q c minimum input edge rate ( ' t/ ' v) v in 0.8v to 2.0v, v cc 3.0v 10 ns/v symbol parameter conditions v cc min max units (v) v ih high level input voltage 2.7 - 3.6 2.0 v 2.3 - 2.7 1.6 1.65 - 2.3 0.65 u v cc 1.4 - 1.6 0.65 u v cc 1.2 0.65 u v cc v il low level input voltage 2.7 - 3.6 0.8 v 2.3 - 2.7 0.7 1.65 - 2.3 0.35 u v cc 1.4 - 1.6 0.35 u v cc 1.2 0.15 x v cc v oh high level output voltage i oh 100 p a 2.7 - 3.6 v cc 0.2 v i oh 12 ma 2.7 2.2 i oh 18 ma 3.0 2.4 i oh 24 ma 3.0 2.2 i oh 100 p a 2.3 - 2.7 v cc 0.2 i oh 6 ma 2.3 2.0 i oh 12 ma 2.3 1.8 i oh 18 ma 2.3 1.7 i oh 100 p a 1.65 - 2.3 v cc 0.2 i oh 6 ma 1.65 1.25 i oh 100 p a 1.4 - 1.6 v cc 0.2 i oh 2 ma 1.4 1.05 i oh 100 p a1 . 2 v cc 0.2
5 www.fairchildsemi.com 74VCX16373 dc electrical characteristics (continued) note 7: outputs disabled or 3-state only. ac electrical characteristics (note 8) symbol parameter conditions v cc min max units (v) v ol low level output voltage i ol 100 p a 2.7 - 3.6 0.2 v i ol 12 ma 2.7 0.4 i ol 18 ma 3.0 0.4 i ol 24 ma 3.0 0.55 i ol 100 p a 2.3 - 2.7 0.2 i ol 12 ma 2.3 0.4 i ol 18 ma 2.3 0.6 i ol 100 p a 1.65 - 2.3 0.2 i ol 6 ma 1.65 0.3 i ol 100 p a 1.4 - 1.6 0.2 i ol 2 ma 1.4 0.35 i ol 100 p a 1.2 0.05 i i input leakage current 0 d v i d 3.6v 1.2 - 3.6 r 5.0 p a i oz 3-state output leakage 0 d v o d 3.6v 1.2 - 3.6 r 10.0 p a v i v ih or v il i off i power-off leakage current 0 d (v i , v o ) d 3.6v 0 10.0 p a i cc quiescent supply current v i v cc or gnd 1.2 - 3.6 20.0 p a v cc d (v i , v o ) d 3.6v (note 7) 1.2 - 3.6 r 20.0 ' i cc increase in i cc per input v ih v cc 0.6v 2.7 - 3.6 750 p a symbol parameter conditions v cc t a 40 q c to 85 q c, units figure (v) min max number t phl , t plh propagation delay c l 30 pf, r l 500 : 3.3 r 0.3 0.8 3.0 ns figures 1, 2 le to o n 2.5 r 0.2 1.0 3.9 1.8 r 0.15 1.5 7.8 c l 15 pf, r l 2k : 1.5 r 0.1 1.0 15.6 ns figures 7, 8 1.2 1.5 39.0 t phl , t plh propagation delay c l 30 pf, r l 500 : 3.3 r 0.3 0.8 3.0 ns figures 1, 2 i n to o n 2.5 r 0.2 1.0 3.4 1.8 r 0.15 1.5 6.8 c l 15 pf, r l 2k : 1.5 r 0.1 1.0 13.6 ns figures 7, 8 1.2 1.5 34.0 t pzl , t pzh output enable time c l 30 pf, r l 500 : 3.3 r 0.3 0.8 3.5 ns figures 1, 3, 4 2.5 r 0.2 1.0 4.6 1.8 r 0.15 1.5 9.2 c l 15 pf, r l 2k : 1.5 r 0.1 1.0 18.4 ns figures 7, 9, 10 1.2 1.5 46.0 t plz , t phz output disable time c l 30 pf, r l 500 : 3.3 r 0.3 0.8 3.5 ns figures 1, 3, 4 2.5 r 0.2 1.0 3.8 1.8 r 0.15 1.5 6.8 c l 15 pf, r l 2k : 1.5 r 0.1 1.0 13.6 ns figures 7, 9, 10 1.2 1.5 34.0 t s setup time c l 30 pf, r l 500 : 3.3 r 0.3 1.5 ns figures 1, 6 2.5 r 0.2 1.5 1.8 r 0.15 2.5 c l 15 pf, r l 2k : 1.5 r 0.1 3.0 ns figures 6, 7 1.2 6.0
www.fairchildsemi.com 6 74VCX16373 ac electrical characteristics (continued) note 8: for c l 50 p f, add approximately 300 ps to the ac maximum specification. note 9: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either h igh-to-low (t oshl ) or low-to-high (t oslh ). dynamic switching characteristics capacitance symbol parameter conditions v cc t a 40 q c to 85 q c, units figure (v) min max number t h hold time c l 30 pf, r l 500 : 3.3 r 1.0 1.0 ns figures 1, 6 2.5 r 0.2 1.0 1.8 r 0.15 1.0 c l 15 pf, r l 2k : 1.5 r 0.1 1.2 ns figures 6, 7 1.2 3.6 t w pulse width c l 30 pf, r l 500 : 3.3 r 0.3 1.5 ns figures 1, 4 2.5 r 0.2 1.5 1.8 r 0.15 4.0 c l 15 pf, r l 2k : 1.5 r 0.1 4.0 ns figures 4, 7 1.2 8.0 t oshl output to output skew c l 30 pf, r l 500 : 3.3 r 0.3 0.5 ns t oslh (note 9) 2.5 r 0.2 0.5 1.8 r 0.15 0.75 c l 15 pf, r l 2k : 1.5 r 0.1 1.5 1.2 1.5 symbol parameter conditions v cc t a 25 q c units (v) typical v olp quiet output dynamic peak v ol c l 30 pf, v ih v cc , v il 0v 1.8 0.25 v 2.5 0.6 3.3 0.8 v olv quiet output dynamic valley v ol c l 30 pf, v ih v cc , v il 0v 1.8 0.25 v 2.5 0.6 3.3 0.8 v ohv quiet output dynamic valley v oh c l 30 pf, v ih v cc , v il 0v 1.8 1.5 v 2.5 1.9 3.3 2.2 symbol parameter conditions t a 25 q c units typical c in input capacitance v cc 1.8v, 2.5v or 3.3v, v i 0v or v cc 6.0 pf c out output capacitance v i 0v or v cc , v cc 1.8v, 2.5v or 3.3v 7.0 pf c pd power dissipation capacitance v i 0v or v cc , f 10 mhz, 20.0 pf v cc 1.8v, 2.5v or 3.3v
7 www.fairchildsemi.com 74VCX16373 ac loading and waveforms (v cc 3.3v 0.3v to 1.8v 0.15v) figure 1. ac test circuit figure 2. waveform for inverting and non-inverting functions figure 3. 3-state output high enable and disable times for low voltage logic figure 4. 3-state output low enable and disable times for low voltage logic figure 5. propagation delay, pulse width and t rec waveforms figure 6. setup time, hold time and recovery time for low voltage logic test switch t plh , t phl open t pzl , t plz 6v at v cc 3.3 r 0.3v; v cc x 2 at v cc 2.5 r 0.2v; 1.8v r 0.15v t pzh , t phz gnd symbol v cc 3.3v r 0.3v 2.5v r 0.2v 1.8v r 0.15v v mi 1.5v v cc /2 v cc /2 v mo 1.5v v cc /2 v cc /2 v x v ol 0.3v v ol 0.15v v ol 0.15v v y v oh 0.3v v oh 0.15v v oh 0.15v
www.fairchildsemi.com 8 74VCX16373 ac loading and waveforms (v cc 1.5 0.1v to 1.2v) figure 7. ac test circuit figure 8. waveform for inverting and non-inverting functions figure 9. 3-state output high enable and disable times for low voltage logic figure 10. 3-state output low enable and disable times for low voltage logic test switch t plh , t phl open t pzl , t plz v cc x 2 at v cc 1.5 r 0.1v t pzh , t phz gnd symbol v cc 1.5v r 0.1v v mi v cc /2 v mo v cc /2 v x v ol 0.1v v y v oh 0.1v
9 www.fairchildsemi.com 74VCX16373 physical dimensions inches (millimeters) unless otherwise noted 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga54a (preliminary)
www.fairchildsemi.com 10 74VCX16373 low voltage 16-bit transparent latch with 3.6v tolerant inputs and outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 fairchild does not assume any responsibility for use of any circuitry described, no circ uit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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